IP Design Director

Job Description

IP Design Director

Top40 Semiconductor Organization in the world

Bangalore

Role Overview

We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions

Key Responsibilities

\n
• Design and implement high-performance digital solutions, including RTL development and synthesis.
\n
• Collaborate with cross-functional teams on IP integration for processor IPs and peripherals
\n
• Deep knowledge of processor boot process and peripheral implementation with boot firmware inmind
\n
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤
\n
• 16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon d
\n
• ebug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification
\n

flows

Basic Qualifications / ExperienceLevel

\n
• Bachelor’s in Electronics/Electrical engineering (Master's preferred).
\n
• Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation.
\n
• Proven expertise in RTL development, synthesis, and timing closure.
\n
• Experience with front-end design, gate-level simulations, and design verification.
\n
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.Required
\n

Expertise

Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advaned nodes (Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles .

Hands-on experience with processor IP

(ARM/ARC)Experience of working on PCIe

is a must.

Hands-on pre-silicon and post-silicon implementing peripherals for I2

C/SPI/UART

Hands-on experience with complex DMA engines and FW interaction.

Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).

Experience with block-level and full-chip design at advanced nodes

(≤ 16nm).

Silicon bring-up and post-silicon debug experience.

Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification.

Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Preferred Experience

\n
• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus.
\n
• Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems
\n
• Experience of working on PCIe/UAL
\n
• is a big plus.Understanding of PAD design, DFT, and floor planning.
\n
• Experience in synthesis, and timing closureis a big plus.
\n
• Experience with NIC, switch, or storage product development.
\n
• Familiarity with working in design and verification workflows in a CI/CD environment.
\n

Skils

microarchitecture

"rtl design" / "RTL coding" /

"RTL Development" /"Logic design"

Synthesis

"timing closure"

ARM/ ARC / RISC-V

PCIe

Verilog

Systemverilog (SV )

UVM

UAL (UALink)

NIC

Switch / Ethernet / "ultra ethernet"

nvlink

"Digital design"

DMA

"ip design"

"ip development"

"ip integraton"

Contact:Uday

Mulya Technologies

muday_

bhaskar@yahoo.com