Job Description
Memory Layout Engineer | ACL Digital
Location: Bangalore
⏳ Experience: 7 Years
⏱️ Notice Period: 0–30 Days
We are hiring an experienced Memory Layout Engineer to design and optimize high-density memory architectures (SRAM/DRAM/HBM/Flash) on advanced sub-5nm process nodes (FinFET/GAAFET). In this role, you will lead custom block floorplanning, execute matched differential routing for word/bit lines, and ensure zero-error physical verification (DRC, LVS, ERC). You will collaborate closely with circuit design teams to apply critical DFM/DFY rules for EUV lithography while leveraging SKILL/TCL/Python scripting to drive memory compiler automation. If you possess 7 years of hands-on expertise with Cadence Virtuoso and Siemens Calibre, send your updated resume to janagaradha.n@acldigital.com to join our cutting-edge silicon team.